In large digital logic systems, reference clocks are used to synchronize and coordinate the transmission of digital logic signals between digital logic devices. The digital logic system will function properly only when all the signals used by the system have defined logic states. This is particularly true on system busses such as memory data and address busses. The logic state of certain signals may be defined only at specific times, for example, the logic state of data signals generated by a random access memory, RAM, may only be defined after a memory access delay.
A computer, a typical digital logic system, accesses memory by performing the following steps. First, the computer supplies an address to the memory address bus. At a predetermined fixed period of time later the address bus stabilizes and the address is defined. Second, address decode logic using the address from the address bus converts the address into a particular RAM cell and a predetermined period of time later transfers the contents of the memory cell to a memory data bus. This period of time is known as the RAM access time. Finally, the data bus signals must be permitted to stabilize before the computer may use the data.
A typical computer will attempt to perform a complete memory access within two reference clock cycles. The computer will have a reference clock with a period 2t. The computer will supply the address and address access signal to memory address bus at time 0t, clock the contents of RAM onto the memory data bus at time 3t, and latch the RAM contents into the computer from the memory data bus at time 4t. This approach works well as long as the RAM access time, m, is less than or equal to the time 4t. If slower, less expensive RAM with an access time of greater than 4t is used, a serious problem develops because no clock edge of the reference clock can be used to transfer the data read from the data bus at time 4t.
Various prior art solutions have been used to address this problem. First, a slower reference clock may be used. The clock frequency is reduced to the point where the RAM access time is again less than or equal to the period 2t. This of course reduces the throughput of the entire digital logic system and is therefore undesirable.
A second solution is to use a higher frequency clock. A clock with considerably higher frequency will have additional edges from which a designer may choose an edge to clock the address into the RAM and address decode logic and still have a clock edge available for transferring the data read from the RAM onto the data bus within the required time. However, higher clock frequencies cause other problems, for example, increased system power, radio frequency interference and clock skew. Clock skew refers to the phase shift of the reference clock as it is transmitted throughout the digital system. The higher the clock frequency, the higher the percentage of the clock period potentially affected by clock skew. Therefore, clock skew with higher frequency clocks is more likely to cause the system to malfunction.
A third solution is to use a technique which delays one or more edges of the reference clock. This technique includes using an RC circuit or delay line to delay the reference clock. This technique, however, has problems with accuracy and sensitivity to temperature and process variations which cause the delay generated to vary. Any variation in the delay may cause the digital logic system to malfunction.
A fourth solution is to use a local frequency multiplier or phase lock loop to generate the higher frequency clock signal with its addition timing edges. These solutions, while generating the needed additional edges at a stable frquency do not provide the precise phase control with respect to the reference clock and therefore require some additional synchronizing scheme to maintain a stable reference to the reference clock.
A fifth solution is to use an asychronous interface with an arbitrator that synchronizes the memory signals to the nearest clock edge in the synchronous system. If an asynchronous signal occurs too close to a clock edge, the arbitrator will delay the signal to the next clock edge. Therefore, the system must tolerate a delay of an entire clock cycle. This method is unacceptable for high performance synchronous memory systems and the like.
A need exists for an accurate, stable, predictable, flexible, and temperature and process independent means for generating additional clock edges from a reference clock signal.